Digital Design, SOC Integration Lead

Meta’s Reality Labs is seeking a Digital Design, SOC Integration Lead to serve as a technical lead for Machine Learning IP integration. In this role, you will drive the integration of Machine Learning IP blocks into complex system-on-chip designs, bringing together expertise in design, integration, and physical design. You will be responsible for project planning, tracking, and execution while working closely with cross-functional teams, SoC teams, and IP vendors to deliver next-generation ML accelerators that power Meta's AR and VR devices.

Responsibilities

• Serve as the technical lead for ML IP integration, driving end-to-end integration from RTL to physical design handoff
• Own project planning, tracking, and execution for ML IP integration efforts
• Lead design and integration activities, including microarchitecture, RTL design, lint, CDC, synthesis, and physical design collaboration
• Partner with cross-functional teams, SoC teams, and external IP vendors to ensure a seamless integration
• Define and drive integration methodologies, flows, and best practices across the silicon team
• Drive root cause analysis and resolution of issues across design, synthesis, and physical implementation stages
• Mentor and guide engineers on ML IP integration and design best practices

Minimum qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 12+ years of experience in digital design and IP/SOC integration
• Experience serving as a technical lead for complex IP or SOC integration projects
• Experience with RTL design, integration, lint, CDC, and synthesis flows
• Experience with physical design concepts and collaboration with P.D. teams
• Experience with project planning, tracking, and execution for silicon programs
• Experience working with cross-functional teams and external IP vendors
• Experience with methods for partitioning a solution across hardware and software, evaluating trade-offs such as speed, performance, power, and area
• Experience with scripting languages such as Python, Perl, or Tcl
• Bachelor's degree in Electrical Engineering, Computer Engineering, or relevant field Experience with low-power design techniques and UPF flows
• Master/PhD degree in EE/CS or equivalent areas
• Experience with physical design flows, floorplanning, and timing closure
• Experience with machine learning accelerator hardware design and integration