Design Verification Engineer, Silicon

Meta Reality Labs is building custom silicon to power the next generation of augmented and virtual reality devices, including headsets and wearables. As a Design Verification Engineer on the silicon team, you will be responsible for ensuring the functional correctness and quality of complex custom chips that enable immersive AR/VR experiences. In this role, you will develop and execute comprehensive verification strategies for digital logic blocks and subsystems, working closely with design, architecture, and software teams to bring high-performance, low-power silicon from specification to tape-out.

Responsibilities

• Develop and own verification plans for digital logic blocks and subsystems within custom AR/VR silicon, covering functional coverage, corner cases, and compliance requirements
• Design and implement constrained-random UVM testbenches to verify complex RTL designs including processors, interconnects, memory controllers, and multimedia accelerators
• Define and close functional coverage models and code coverage metrics to ensure thorough verification of design intent
• Collaborate with RTL design engineers to review microarchitecture specifications and identify verification risks early in the design cycle
• Develop and maintain simulation infrastructure, regression frameworks, and automated test suites to support continuous integration of design changes
• Perform formal verification and property checking on critical design blocks to complement simulation-based verification
• Debug failing simulations and regressions by analyzing waveforms, log files, and RTL code to root-cause design or testbench issues
• Partner with post-silicon validation and firmware teams to develop pre-silicon test content that transitions to hardware bring-up
• Contribute to verification methodology improvements, including reusable verification IP and shared infrastructure across the silicon team
• Track and report verification progress, coverage closure status, and risk areas to design and program management stakeholders

Minimum qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience in digital design verification, including development of UVM-based constrained-random testbenches for complex RTL blocks or subsystems
• 6+ years of experience with hardware description and verification languages including SystemVerilog and/or VHDL
• Experience defining and closing functional coverage models and code coverage metrics for complex digital designs
• Experience debugging RTL simulations using waveform analysis tools and log-based root-cause analysis
• Experience with scripting languages such as Python or Perl for test automation, regression management, or coverage analysis Experience with post-silicon validation, hardware bring-up, or transitioning pre-silicon test content to physical hardware
• Experience verifying silicon for mobile, wearable, or consumer electronics SoCs, including low-power design verification techniques
• Knowledge of AR/VR-relevant subsystems such as Computer Vision , image signal processors, or neural network accelerators
• Familiarity with formal verification tools and methodologies such as property checking or equivalence checking