Wireless SOC Design Verification Engineer

Summary

Apple’s N1 wireless chip powers connectivity across every new iPhone — and its successor is already taking shape. As a Wireless SOC Verification Engineer, you’ll own your verification scope end-to-end — starting with a well-defined block or feature and growing in scope and complexity as you do. Over time, you’ll build depth in the IPs you know best and breadth across others, from block-level verification up toward subsystem and SOC integration.

Description

You’ll own verification for your scope — with a mentor’s guidance as you build toward full ownership — on a chip that ships in every new iPhone, starting with a block or feature sized to where you are and expanding from there. You’ll work across the Power Management Unit, the CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, and peripherals like SPI and UART — primarily through simulation, with exposure to formal verification as you grow. Low-power is part of the picture too: you’ll get hands-on with power intent verification using UPF within your scope. AI is reshaping how the team works, and you’ll help apply AI-assisted tools for test generation, debug, or verification closure as part of your day-to-day.

Responsibilities

• Pair with design early — shape the verification plan before RTL lands, not after.
• Debug corner-case failures and build the models — coverage or proof — that catch them.
• Verify low-power design intent using UPF within your scope.
• Grow into formal verification as your projects call for it — the team will help you ramp up, not expect you to arrive fluent.
• Shape the verification approach for your scope, with a mentor’s guidance — building toward full ownership as that scope grows.
• Verify end-to-end WiFi and Bluetooth traffic flows, from subsystem level up through top-level SOC integration.
• Push on AI-assisted verification — help the team find where it moves the needle.
• Get exposure to post-silicon bring-up when your project reaches that stage.

Minimum Qualifications

• Minimum requirement of a bachelors degree.
• Strong academic record (GPA).
• Proficiency in SystemVerilog.
• Strong analytical thinking and problem-solving skills.

Preferred Qualifications

• Familiarity with UVM methodology.
• Exposure to PCIe, Bus Fabric, NOC, AHB, AXI-based bus architectures in a UVM environment.
• Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC.
• Experience with Formal Verification.
• In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
• Should be a great teammate with excellent communication skills and the desire to seek diverse challenges.