Technical Lead I - VLSI ML SD

Memory Layout JD Key Skills & Responsibilities SRAM bitcell and array layout, including abutment and optimization for area and performance Layout of memory peripherals such as Row/Column Decoders, Sense Amplifiers, Pre-charge, Write Drivers, Read/Write Assist, IO and Self-Timing circuits Experience with Single-Port SRAM, Dual-Port SRAM and ROM architectures Full memory macro floorplanning, block integration and critical signal routing Strong understanding of matching, symmetry, shielding and parasitic-aware layout techniques Layout optimization for area, timing, power and leakage Hands-on experience with DRC, LVS, ERC and parasitic extraction Experience with IR/EM, PERC, antenna and reliability checks is desirable Understanding of power grid design, decoupling capacitance and power sequencing Ability to support post-layout extracted simulations and optimize layout based on circuit/characterization feedback Experience with industry-standard custom layout and physical verification tools Exposure to advanced technology nodes and SRAM compiler development is preferred Experience