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Technical Lead I - VLSI
UST
- 🇮🇳 India
- On-site
- Staff / Principal
- 3 weeks ago
- SystemVerilog
- PCIe
3 weeks ago
Not enough detail in this posting to match
3–7 years of experience having strong expertise in IP Verification, Functional Coverage, Assertions, SystemVerilog (SV), and UVM. Experience with the Ethernet protocol is mandatory, while PCIe experience will be an added advantage.
Technical Lead I - VLSI · UST