Staff Engineer

Staff Engineer – CPU / RTL / Physical Design

Company: Qualcomm
Experience: 4–10 years
Location: Santa Clara, CA / San Diego, CA / Austin, TX
Employment Type: Full-Time

Job Summary

Qualcomm is seeking a highly skilledStaff Engineer with strong experience inCPU design, RTL development, and/or Physical Design (PD) to work on next-generation high-performance, low-power SoCs and CPU architectures.

The ideal candidate will have hands-on experience inASIC/SoC development, strong understanding of CPU microarchitecture and digital design, and the ability to work acrossRTL, synthesis, physical implementation, timing, power, and area optimization. The engineer will collaborate closely with Architecture, RTL, Design Verification, Physical Design, DFT, CAD, Power, and Post-Silicon teams.

Key Responsibilities

• Design and optimize high-performance CPU/SoC blocks frommicroarchitecture through RTL and physical implementation.
• Develop, review, and refineVerilog/SystemVerilog RTL.
• Participate in microarchitecture definition and design trade-offs targetingPower, Performance, and Area (PPA).
• Work closely with Physical Design teams onsynthesis, floorplanning, placement, CTS, routing, timing closure, and signoff.
• Analyze and resolvetiming, congestion, power, area, and design-closure issues.
• Support RTL-to-GDS implementation and identify RTL changes required for physical convergence.
• Perform or supportSTA/MMMC analysis, constraint development, and timing optimization.
• Collaborate with verification teams on functional verification, coverage, debugging, and design quality.
• Work with DFT, CAD, and implementation teams to resolve complex design issues.
• Develop automation and productivity solutions usingPython, Tcl, Perl, or Shell.
• Participate in design reviews and provide technical leadership on critical design problems.
• Mentor junior engineers and contribute to methodology and flow improvements.

Required Qualifications

• Bachelor's or Master's degree inElectrical Engineering, Computer Engineering, Computer Science, or related field.
• 4–10 years of experience in ASIC/SoC, CPU, RTL, or Physical Design.
• Strong understanding ofdigital design and ASIC development flows.
• Hands-on experience withVerilog/SystemVerilog.
• Strong understanding ofCPU/microprocessor architecture is highly preferred.
• Experience with one or more of:
  • RTL design
  • Logic design
  • Synthesis
  • Physical Design
  • Static Timing Analysis
  • Timing closure
  • PPA optimization
  • SoC integration
• Experience working inLinux/Unix environments.
• Strong scripting/programming skills inPython, Tcl, Perl, or Shell.
• Strong debugging, analytical, and problem-solving skills.

Preferred Qualifications

CPU / RTL

• Experience with CPU pipeline architecture, includingFetch, Decode, Rename, Execute, Load/Store, Cache, MMU, or Branch Prediction.
• Experience without-of-order execution, memory hierarchy, or processor microarchitecture.
• Strong RTL coding and microarchitecture implementation experience.
• Knowledge ofCDC, lint, synthesis, formal verification, and low-power design.

Physical Design

• Experience with completeRTL-to-GDSII flow.
• Floorplanning, power planning, placement, CTS, routing, and timing closure.
• Experience withCadence Innovus and/orSynopsys Fusion Compiler.
• Experience withPrimeTime STA.
• MMMC timing analysis and advanced-node implementation.
• Experience withIR drop, EM, signal integrity, crosstalk, ECOs, and physical verification.
• Knowledge ofUPF and low-power implementation.