SI Hardware Manager

Tesla

🇮🇳 India
On-site
Manager or above
3 hours ago

SoCs
SystemVerilog
Verilog
AI
AI/ML

3 hours ago

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What to Expect

About the Role
Tesla is seeking an experienced RTL Lead to drive the front-end design of next-generation SI accelerators, neural processing units (NPUs), and custom SoCs that power Full Self-Driving, Optimus, and our Dojo supercomputer. In this leadership role, you will own RTL architecture and implementation for high-performance, power-efficient digital designs at scale. You’ll lead a team of RTL engineers while collaborating closely with architecture, verification, physical design, and software teams to deliver world-class silicon that pushes the boundaries of SI hardware.

What You’ll Do

Lead the micro-architecture, RTL design (SystemVerilog/Verilog), and integration of complex IP blocks or full subsystems (e.g., tensor cores, interconnect/NoC, memory controllers, data paths, or AI-specific compute clusters).

Drive key design decisions on performance, power, area (PPA), and scalability for multi-billion-gate SI chips.

Mentor and manage a team of RTL designers, providing technical guidance, code reviews, and career development.

Collaborate with Architecture teams to refine specifications and with Verification teams to ensure high-quality, verifiable designs.

Work with Physical Design, DFT, and Emulation teams to close timing, optimize for synthesis, and support tape-out milestones.

Perform RTL quality checks, linting, CDC/RDC analysis, and formal verification.

Contribute to power, performance, and area evaluations through modeling and simulation.

Participate in bring-up, silicon validation, and post-silicon debugging as needed.

What You’ll Bring

Education: BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.

Experience: 15+ years of RTL design experience in complex ASICs (preferably AI/ML accelerators, CPUs, GPUs, or automotive SoCs), with at least 5 years in a technical leadership or lead role.

Strong expertise in SystemVerilog, high-performance digital design, pipelining, arbitration, and power optimization techniques.

Deep knowledge of AMBA/AXI/ACE protocols, NoC architectures, memory subsystems, or SI tensor operations.

Hands-on experience with synthesis (e.g., Synopsys DC), static timing analysis, linting (SpyGlass), and CDC tools.

Proven track record of delivering production silicon from RTL to tape-out.

Excellent problem-solving, communication, and cross-functional collaboration skills.

Passion for Tesla’s mission to accelerate the world’s transition to sustainable energy and autonomous transportation.

SI Hardware Manager · Tesla

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