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Senior Staff Engineer, Digital Verification - ACAS

Leadstack Inc
Location not stated
Staff / Principal
7 months ago
$90 – $100 / hour
  • SystemVerilog
  • Object Oriented Programming
  • C++
  • Python
  • Perl
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Job Description

LeadStack Inc. is an award winning, one of the nation's fastest growing, certified minority owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.



Senior Staff Engineer, Digital Verification - ACAS
Location: San Jose, CA – Onsite
Duration: 6+months
Pay Rate: $90/hr – $100/hr
Vertical: Engineering

 
Description
What You’ll Do
  • Collaborate with RTL Designers and System Architects to define verification specifications.
  • Design test suites for full-chip and block-level verification; develop directed and constrained-random test cases; analyze and debug simulations at RTL and gate levels.
  • Build functional coverage models, collect, and analyze coverage data.
  • Build testbenches for low-power designs; analyze simulations with Hybrid UPF and PG netlists.
  • Manage regression analysis; file and track bugs using bug-tracking systems.
 
Requirements
  • Bachelor’s degree with 15+ years of relevant industry experience, Master’s with 13+ years, or PhD with 10+ years in Electrical Engineering or related field (preferred).
  • Experience developing testbenches using SystemVerilog UVM, including test case development for constrained-random and directed scenarios.
  • Experience in MCU/CPU verification at both processor and sub-system levels.
  • Strong understanding of CPU architectures and instruction sets (x86, ARM, RISC-V variants), including:
    • Core architecture/micro-architecture verification.
    • Multi-processor cache (L2/L3) coherency and memory hierarchy verification.
  • Good object-oriented programming skills in C++/SystemVerilog; scripting in Python/Perl.
  • Familiarity with Formal Verification.
  • DMS Verification experience or knowledge preferred.
  • Excellent simulation debugging and problem-solving skills.
  • Ability to adopt new methodologies/techniques and promote them across the organization.
  • Experience with EDA tools: Simulators (Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, or equivalent); debugging tools (Synopsys Verdi, Cadence SimVision).
 
   know more about current opportunities at LeadStack , please visit us on https://leadstackinc.com/careers/
Should you have any questions, feel free to call me on (513) 3184502 or send an email on
waseem.ahmad@leadstackinc.com
 
 
 

 

 

Senior Staff Engineer, Digital Verification - ACAS · Leadstack Inc

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