Senior Staff DSP Design Engineer, Google Cloud

About the job

As the architect for high-speed data paths, you will define the roadmap for scaling interconnect speeds. You will evaluate and select key technologies such as Co-Packaged Optics (CPO), advanced modulation formats, and new Forward Error Correction (FEC) methods to support future Artificial Intelligence (AI) computing clusters.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
• 12 years of experience in Silicon Architecture, Mixed-Signal DSP, Communication Theory, or Systems Engineering.
• Experience defining architectural specifications for high-bandwidth interconnects.
• Experience with silicon development from initial concept through to high-volume production (Graphic Design System II (GDSII) to market).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience representing organizations in industry standards bodies (e.g., IEEE, OIF, PCIe-SIG, or CXL).
• Understanding of advanced low power DSP implementation.

Responsibilities

• Identify the "limits of physics" for current Digital Signal Processing (DSP) architectures and pivot the team toward next-generation solutions, such as Machine Learning (ML)-based equalization or optical-specific DSP.
• Define the requirements for DSP test chips to validate new architectures in advanced nodes before they hit production.
• Drive the long-term power-reduction roadmap, ensuring our interconnects do not become the thermal bottleneck.
• Represent Google in the Optical Internetworking Forum (OIF) and Institute of Electrical and Electronics Engineers (IEEE) standards, ensuring our hyperscale requirements for latency and power are reflected in global specifications.