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Senior Silicon Design Verification Engineer, Mixed Signal
Google
- 🇺🇸 United States | 🇸🇬 Singapore | 🇮🇳 India | 🇻🇳 Vietnam | 🇦🇺 Australia | 🇹🇼 Taiwan | 🇯🇵 Japan
- On-site
- Senior
- 4 hours ago
- AI
- SystemVerilog
- Verilog
- Python
4 hours ago
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.In most instances, this position requires in-person interviews as part of the hiring process.Google welcomes people with disabilities.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following:New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience leading digital verification using SystemVerilog for ASIC designs.
- Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
- Experience with RTL, low power (UPF/CPF), gate level (GLS) and formal verification techniques.
- Experience with mixed signal (AMS/DMS) designs, mixed mode verification, and writing SystemVerilog models of analog blocks (RNM, Verilog-AMS).
- Experience in creating detailed block-level design verification strategies and plans.
- Experience creating verification components and environments using UVM and SystemVerilog Assertions (SVA).
- Proficiency in scripting languages such as Python.
Responsibilities
- Plan and execute on the verification of digital and mixed signal design blocks by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Identify and implement key coverage metrics for stimulus and corner-cases to identify verification holes and to show progress towards tape-out.
- Work with design verification and other stakeholders to come up with detailed execution plans, schedule, dependencies and deliverables.
- Work closely with system, software, design, DFT and physical implementation stakeholders to make technical decisions.
- Be the primary point of contact for functional verification for cross-functional teams and lead/drive the building of reusable Design Verification (DV) infrastructure components.
Senior Silicon Design Verification Engineer, Mixed Signal · Google