Senior RTL/STA/CDC Engineer

.Job Title: Senior RTL/STA/CDC Engineer

Location:Bay Area, CA
Duration: Contract
Experience: 7+ Years

Job Summary:

We are looking for a strong RTL Design Engineer with deep expertise in CDC analysis, Static Timing Analysis (STA), and timing constraints development. The ideal candidate will drive timing closure activities and ensure robust clock-domain crossing implementations for complex SoC designs.

Key Responsibilities:

• Develop and analyze RTL designs for SoC/IP development.
• PerformClock Domain Crossing (CDC) analysis and resolution.
• Create and validateSDC timing constraints for complex designs.
• Execute and supportStatic Timing Analysis (STA) activities through timing signoff.
• Collaborate with design and implementation teams to achieve timing closure.
• Review and improve synchronization strategies across clock domains.
• Support low-power design verification activities.

Required Skills:

• 7+ years of experience in digital design engineering.
• Strong expertise inRTL Design, CDC, STA, and Timing Constraints.
• Hands-on experience withQuesta CDC and CDC methodologies.
• Strong understanding ofStatic Timing Analysis and timing signoff fundamentals.
• Proficiency inVerilog/SystemVerilog.
• Experience with front-end tools includingVerilog simulators, CDC checkers, lint tools, and low-power static checkers.
• Knowledge ofclock crossing techniques and synchronization schemes.
• Familiarity withSpyGlass Lint, VCS, and other verification tools.
• Understanding ofUPF (Unified Power Format) and low-power intent verification.

Preferred Qualifications:

• Experience withPCIe protocols and high-speed digital interfaces.
• Knowledge ofAXI, APB, and other industry-standard protocols.
• Familiarity withARM Fabric IPs andIP-XACT.
• Understanding ofNoC tools and architecture concepts.
• Scripting knowledge inPython, Tcl, or Perl.

Education:

• Bachelor's or Master's degree in Electrical Engineering or related field.