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Senior Physical Design Engineer (ASIC Digital Implementation)
Apolis
- 🇮🇳 India
- Hybrid
- Senior
- 1 day ago
- $20 – $25 / hour
- SoCs
- Foundry
- Python
- Perl
- Node.js
1 day ago
Position Summary
We are seeking a hands-on Senior Physical Design Engineer with a minimum of 5 years of ASIC implementation experience to support the development and tapeout of advanced digital and mixed-signal SoCs for wireless solution.
The successful candidate will be responsible for digital implementation from synthesized netlist through final GDSII release, including floorplanning, power planning, place-and-route, clock-tree synthesis, timing closure, physical verification, power integrity analysis, and tapeout signoff.
This role requires close collaboration with RTL, DFT, verification, layout, and system teams to achieve aggressive schedule, performance, power, and area targets.
Key Responsibilities
- Drive block-level and full-chip physical design implementation from netlist to GDSII.
- Develop and execute floorplanning, power planning, placement, clock-tree synthesis (CTS), routing, and physical optimization flows.
- Own timing closure across multiple operating modes including functional, scan shift, and scan capture modes.
- Develop, optimize, and maintain CTS methodologies and scripts to support complex clock architectures and scan requirements.
- Perform static timing analysis (STA) and resolve setup, hold, clock skew, insertion delay, transition, and timing constraint violations.
- Drive physical verification closure including DRC, LVS, antenna, ERC, and density checks.
- Perform power integrity and EMIR analysis and drive design modifications required for signoff closure.
- Support Formality and equivalence checking throughout the implementation flow.
- Collaborate with DFT engineers to ensure successful implementation of scan, MBIST, ATPG, and test structures.
- Work with RTL designers to resolve implementation, timing, congestion, and power issues.
- Support integration of large digital subsystems including embedded processors, memories, and custom digital logic.
- Debug implementation flow issues and improve methodology through automation and scripting.
- Participate in block-level and top-level timing closure activities and drive signoff readiness.
- Coordinate final tapeout activities and ensure compliance with foundry signoff requirements.
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
- Minimum 5 years of industry experience in ASIC physical design and implementation.
- Proven experience participating in successful ASIC or SoC tapeouts.
- Strong understanding of:
- Floorplanning and macro integration
- Power planning and power-grid design
- Place-and-route optimization
- Clock-tree synthesis and clock distribution
- Multi-mode, multi-corner timing closure
- Static timing analysis
- Physical verification
- EMIR and power integrity analysis
- Design-for-test implementation concepts
- Experience with industry-standard EDA tools such as:
- Cadence Innovus
- Cadence Tempus
- Synopsys ICC2
- Synopsys PrimeTime
- Siemens Calibre or Cadence Pegasus
- RedHawk, Voltus, or equivalent EMIR tools
- Strong Tcl scripting skills and familiarity with Python, Perl, or shell scripting.
- Excellent debugging, problem-solving, and communication skills.
- Experience implementing large SoCs containing embedded CPUs, RISC-V processors, memory subsystems, and scan architectures.
- Experience with advanced-node technologies.
- Familiarity with low-power implementation methodologies including UPF/CPF flows.
- Experience with hierarchical and full-chip implementation.
- Experience supporting wireless communication, radar, networking, or high-performance compute products.
- Experience working with mixed-signal SoCs containing RF and analog subsystems.
Senior Physical Design Engineer (ASIC Digital Implementation) · Apolis