AL
RTL Design Engineer
Artech LLC
🇬🇧 United Kingdom | 🇺🇸 United States
On-site
4 weeks ago
$60 – $95 / hour
- Verilog
- Python
4 weeks ago
Not enough detail in this posting to match
Location: North Reading, MA
Duration: 12 months (Temp to Perm)
Payrate: $60 to $95 per hour
Job Description:
You will join a best-in-class Digital team as RTL Designer working in collaboration with an Analog team and product architects to develop client’s next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bringup, and will have cutting-edge AI tools available to optimize your productivity.
Responsibilities:
- Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect
- Integration of industry standard and client custom IPs
- Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success
- Providing timing constraints and STA support to the Physical Design team through timing closure
- Providing post silicon lab bringup and debug support
Must Have:
- BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
- Extensive logic design experience writing RTL in Verilog
- Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT
- Experience with logic synthesis and timing constraints
- Experience with clock domain crossings (CDC) and static timing analysis (STA)
- Experience with high speed memory and serial
- Experience with automation through scripting such as Python, Tcl & Make
RTL Design Engineer · Artech LLC