Lead DFT Engineer

Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan insertion flows during synthesis.  Should have proficiency in industry-standard DFT tools such asMentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test. Should be able to contribute to ATPG at partition and SoC level. . Should have experience withDFT GLS simulation tools and methodologies, including fault modeling andcoverage analysis. Should be familiar with industry standards such asIEEE 1149.1 (JTAG) andIEEE 1687 (IJTAG).Effective communication and teamwork skills, with the ability to collaborate across functions.

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