Likeremote

Subscribe to the latest remote jobs:

  • Likeremote jobs on https://LinkedIn.com/
  • Likeremote jobs on https://telegram.org/
  • Likeremote jobs on Reddit.com
NXP USA Inc. logo

PRINCIPAL PHYSICAL VERIFICATION ENGINEER

NXP USA Inc.
  • ๐Ÿ‡ฎ๐Ÿ‡ณ India
  • On-site
  • Staff / Principal
  • 2 days ago
  • Foundry
  • CAD

Not enough detail in this posting to match

We are seeking a talentedPhysical Verification Design Engineerto join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.

Key Responsibilities

  • Performphysical verification (PV) for block-level and full-chip designs, including:
    • Design Rule Check (DRC)
    • Layout Versus Schematic (LVS)
    • Electrical Rule Check (ERC)
    • Antenna, density, and reliability checks
  • Drivesignoff closure by identifying and resolving PV violations efficiently.
  • Work withphysical design and layout teams to debug and fix violations.
  • Develop and maintainrunsets, decks, and automation flows using industry-standard tools.
  • Analyzefoundry decks and PDK updates, ensuring compliance with process requirements.
  • Leadtapeout readiness reviews and ensure high-quality database delivery.
  • Performhierarchical verification and regression management.
  • Participate in improvingverification methodologies, runtime, and capacity optimization.
  • Interface withfoundry and EDA vendors to resolve tool or deck-related issues.
  • Mentor junior engineers and review their work as needed.

Preferred / Added Advantage Skills

  • Exposure toPhysical Design (PD) concepts, including:
    • Floorplanning (macro placement, block shaping, congestion awareness)
    • Power Delivery Network (PDN) design (power grid, IR drop considerations)
  • Understanding of:
    • Placement, CTS, routing flows
    • PD-PV interaction and impact of layout decisions on DRC/LVS closure
  • Knowledge of:
    • EM/IR, latch-up, ESD reliability checks
    • Multi-patterning / EUV constraints
  • Experience withfull-chip integration and SoC-level challenges
  • Ability tocorrelate PV issues with PD root causes (e.g., spacing, density, routing hotspots)
  • Exposure toflow automation and methodology development

Soft Skills

  • Strong analytical and problem-solving ability
  • Effective communication across cross-functional teams
  • Ownership mindset with focus onquality and timelines
  • Ability to work independently and guide team members


More information about NXP in India...

#LI-29f4

PRINCIPAL PHYSICAL VERIFICATION ENGINEER ยท NXP USA Inc.

Auto apply with Likeremote