Internship - FPGA Hardware Design - PQ Cryptography Hardware Accelerator

Who we are

CryptoNext Security is a deeptech startup specializing in post-quantum cryptography. Our solutions help businesses and institutions prepare for a future where quantum computers will challenge traditional data security. We work with leading clients in finance, defense, and telecommunications.

About the role

As part of an exploratory project onhardware accelerators for post-quantum cryptography (PQC), we are looking for a highly motivatedFPGA Hardware Design Engineer to take ownership of a key strategic project at the intersection ofhardware/software codesign (FPGA development and low-level C) andpost-quantum cryptographic accelerators. You will work on the design, integration, and evaluation of hardware accelerators for well-identified mathematical functions used in post-quantum cryptographic algorithms, with a strong focus on demonstrating concrete performance benefits on a real embedded platform.

Your mission

You will study state-of-the-art approaches described in the scientific literature on PQC hardware acceleration, including relevant academic work such asthis recent study, and implement the selected ones. You will focus in particular on theNumber Theoretic Transform (NTT) and theKeccak state permutation function, two key computational functions involved in the implementation of algorithms such as ML-KEM and ML-DSA (lattice-based PQC algorithms).

You will be responsible fordeveloping system-level RTL code using SystemVerilog, integrating the resulting accelerators into a complete hardware/software system, and evaluating their impact on application-level performance. The target platform will be anAMD Xilinx ZCU104 development board, equipped with aZynq UltraScale+ MPSoC.

The primary objective of the internship is to demonstrate, on the target platform, that a hardware accelerator for either theNTT or theKeccak permutation can effectively accelerate the correspondingML-KEM orML-DSA implementation in theCryptoNext Quantum Safe Library (C-QSL).

Required skills

Must-have

• FPGA development, RTL design using Verilog, SystemVerilog or VHDL
• Experience withAMD Vivado orIntel Altera Quartus and FPGA development platforms
• Good programming skills inC underLinux, with basic knowledge of assembly language
• Strong interest in hardware/software codesign and embedded systems
• Experience withGit and standard software development workflows
• Familiarity withshell scripting,Makefiles, and compiler toolchains
• Experience usingprofilers and debuggers to analyze and optimize software performance
• Ability to work independently, investigate technical problems, and communicate results clearly

Nice-to-have

• Knowledge ofAMBA protocols, such asAXI, AHB, APB, or CHI
• Experience withJTAG-based debugging
• Experience withQEMU, including theXilinx fork of QEMU
• Experience withQEMU/SystemC/Verilator co-simulation
• Previous exposure topost-quantum cryptography, lattice-based cryptography,ML-KEM,ML-DSA, NTT or DFT, or Keccak (or more generally hash functions)
• Familiarity with embedded Linux andZynq UltraScale+ MPSoC architectures

Internship details

• Duration: 6 months
• Period: December 2026 – June 2027
• Education: Final-year engineering student orM2 / Master's degree in computer engineering, electrical engineering, embedded systems, microelectronics, or a related field