Memory Design Interface Architect, Terafab

What to Expect

We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot. 

In this role, you will own HBM IO blocks and the subsystems around them from spec to tape-out to bring-up. That includes the PHY, controller-to-PHY, die-to-die, clocking, training, and electrical interfaces that support future interfaces. The work collaborates closely with the AI Hardware team, the people who define the workloads and the people who package the die. 

What You’ll Do

• Own HBM IO blocks and subsystems from architecture through circuit and RTL implementation, verification, tape-out, bring-up, and post-silicon debug 
• Set the requirements for the HBM PHY, controller-to-PHY, die-to-die links, clocking, training, calibration, power management, error handling, and test, including support for future interface technologies  
• Make the bandwidth, latency, power, area, reliability, signal integrity, power integrity, yield, and manufacturability trade-offs, and hold the line on them 
• Design the analog, mixed-signal, and digital interface functions inside the high-speed memory subsystem 
• Work with package, interposer, physical design, signal integrity, power integrity, and thermal to close the interface across 2.5D and 3D assemblies 
• Lead root-cause on the hard bugs: circuit, RTL, architecture, process, package, interposer, and system, pre-silicon and post-silicon 
• Run one or more interface programs. Set the spec, the plan, the risks, and the schedule, and keep architecture, design, layout, verification, validation, packaging, test, and product engineering on that plan 
• Work with internal teams, IP providers, foundries, and partners to integrate high-speed memory and die-to-die interfaces 
• Push the next HBM, chiplet, and heterogeneous-integration architectures against Tesla’s training and inference workloads 
• Mentor engineers in architecture reviews, build reviews, and debug. Tighten the methods, the guidelines, and what we reuse 

What You’ll Bring

• 15+ years in HBM, DDR, LPDDR, high-speed PHY, mixed-signal, SoC, or ASIC design, or equivalent experience 
• Degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience 
• Experience taking complex interface IP or a subsystem from architecture through silicon bring-up and post-silicon debug 
• Deep experience in high-speed memory-interface architecture and design. HBM product families preferred 
• Analog and mixed-signal circuit design, digital microarchitecture, RTL, clocking, training, calibration, power management, and error handling 
• Front-end implementation and verification: synthesis, static timing, logic equivalence, and RTL debug 
• Experience leading technical execution across disciplines and sites 
• Working knowledge of DRAM operation, HBM and DDR, JEDEC, and memory subsystems