RC
Lead Product Engineer – Genus Synthesis & Physical Design
RAPS Consulting - India
🇮🇳 India
On-site
Staff / Principal
2 weeks ago
- Node.js
- Perl
- Python
- Verilog
- SystemVerilog
2 weeks ago
Location: Noida / Bangalore, India
Experience: 4–6 Years
About the Role
Cadence is seeking a highly motivatedLead Product Engineer to join our Digital Design & Signoff Solutions team. In this role, you will work closely with R&D, Application Engineering, and semiconductor customers to drive the development, validation, and deployment of next-generationlogic synthesis, physical-aware synthesis, and timing optimization technologies.
You will play a key role in enabling best-in-classPower, Performance, and Area (PPA) for advanced ASIC and SoC designs across cutting-edge process nodes. This is an excellent opportunity for engineers passionate aboutSynthesis, Physical Design, Static Timing Analysis (STA), and Timing Closure to influence industry-leading EDA products used by the world's top semiconductor companies.
Key Responsibilities
- Perform Product Engineering activities for CadenceGenus Synthesis Solution, focusing on synthesis, physical-aware optimization, and timing closure technologies.
- Evaluate and validate new features, algorithms, and enhancements developed by the R&D team.
- Drive complex experiments and benchmark studies to optimize QoR, runtime, power, timing, and area metrics.
- Analyze and debug synthesis, physical implementation, and timing closure issues on advanced node designs.
- Work closely with customers, field application engineers, and R&D teams to resolve challenging design and flow-related problems.
- Develop and validate complete implementation flows involvingGenus, Innovus, Tempus, and related Cadence tools.
- Understand customer requirements and contribute to product enhancements, feature definitions, and Product Requirement Specifications (PRS).
- Collaborate with engineering teams to improve interoperability between synthesis, place-and-route, and signoff flows.
- Perform root-cause analysis for complex design convergence, timing, and physical implementation challenges.
- Create automation scripts, methodologies, and best practices to improve productivity and scalability.
- B.E./B.Tech/M.E./M.Tech/MS in Electronics, VLSI, Computer Engineering, or related field.
- 4–6 years of industry experience in Digital Implementation, Product Engineering, Physical Design, or Application Engineering.
- Strong understanding ofLogic Synthesis, Physical Design, STA, and Timing Closure.
- Hands-on experience with advanced technology nodes (28nm and below, preferably 16nm/7nm/5nm).
- Experience with industry-standard EDA tools, preferably:
- Cadence Genus
- Cadence Innovus
- Cadence Tempus
- Synopsys DC/PT/ICC2 (good to have)
- Strong knowledge of:
- RTL-to-GDSII implementation flow
- Timing analysis and signoff
- Physical-aware synthesis
- Constraints development and optimization
- Multi-mode multi-corner (MMMC) methodologies
- Low-power design techniques
- Experience debugging timing, logic, and physical implementation issues.
- Scripting expertise inTCL, Perl, Python, or Shell.
- Working knowledge of Verilog/SystemVerilog.
- Product Engineering or Customer Support experience within the EDA industry.
- Exposure to advanced timing closure methodologies and physical optimization techniques.
- Knowledge of Formal Verification and Low-Power implementation flows.
- Strong problem-solving and analytical mindset.
- Excellent communication skills with the ability to collaborate across global teams and customer engagements.
- Opportunity to work on industry-leading EDA technologies powering next-generation semiconductor designs.
- Exposure to cutting-edge process nodes and complex SoC implementation challenges.
- Direct collaboration with world-class R&D teams and leading semiconductor customers worldwide.
- A fast-paced environment focused on innovation, technical excellence, and career growth.
Lead Product Engineer – Genus Synthesis & Physical Design · RAPS Consulting - India