Senior STA Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more atwww.asteralabs.com.

Senior STA Engineer – Job Description

Position: Senior STA Engineer
Experience: 4–8 years
Location: Ahmedabad
Employment Type: Full-time

Job Summary

We are looking for aSenior STA Engineer with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues.

Key Responsibilities

• OwnSTA and timing signoff activities from synthesis through physical design and tape-out.
• PerformMCMM/MMMC timing analysis across all functional and test modes.
• Analyze and debugsetup, hold, recovery, removal, min/max, and clock-related violations.
• Develop, review, and validateSDC constraints, including clocks, generated clocks, I/O delays, false paths, multicycle paths, and timing exceptions.
• Perform detailedclock tree and clock timing analysis, including skew, latency, uncertainty, jitter, and clock reconvergence.
• Drivetiming closure in collaboration with RTL, synthesis, physical design, and ECO teams.
• Analyze critical timing paths and recommend design, synthesis, placement, routing, or ECO solutions.
• Perform timing analysis consideringOCV/AOCV/POCV, derates, SI/crosstalk, and process-voltage-temperature variations.
• Review timing constraints and methodology to ensuresignoff-quality timing analysis.
• Supporttiming ECOs and evaluate their impact across multiple corners and modes.
• Develop and maintainTcl/Python automation for STA analysis, report generation, and flow optimization.
• Debug complex timing issues and provide technical guidance to junior STA engineers.
• Participate in methodology development, flow improvements, and timing signoff reviews.
• Coordinate with cross-functional teams to ensure project milestones andtape-out schedules are achieved.

Required Technical Skills

• Strong expertise inStatic Timing Analysis and timing closure.
• Hands-on experience withSynopsys PrimeTime, Cadence Tempus, or equivalent STA tools.
• Excellent knowledge ofSDC constraints and timing exceptions.
• Strong understanding ofASIC/SoC design, synthesis, physical design, and signoff flows.
• Expertise inMCMM/MMMC analysis.
• Good understanding ofOCV/AOCV/POCV, CPPR, SI/crosstalk, derating, and variation-aware timing.
• Strong knowledge of clock-domain timing, clock uncertainty, skew, latency, and clock reconvergence.
• Proficiency inTcl scripting; Python/Perl scripting is an advantage.
• Strong debugging, analytical, and problem-solving skills.

Senior-Level Expectations

• Ability toindependently own STA for a block or full-chip design.
• Ability to identify root causes of complex timing violations and drive them to closure.
• Ability to interact effectively withdesign, RTL, synthesis, PD, CTS, and signoff teams.
• Experience mentoring junior engineers and reviewing their STA work.
• Strong ownership, communication, and project-management skills.
• Ability to work in a fast-paced semiconductor environment and deliver against tight tape-out schedules.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, VLSI, or a related discipline.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.