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FT

FPGA Design/Verification Engineer

First Tek, Inc.
🇺🇸 United States
On-site
3 weeks ago
  • FPGA
  • Verilog
  • SystemVerilog
  • System Design
  • AI
  • Secret Clearance
3 weeks ago
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Description: The selected candidate will be responsible for ASIC & FPGA development on R&D program. This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms. Experience with COTS based control platforms and embedded processors on FPGA platforms. This person will help develop more affordable ways to automate and develop scripts to improve FPGA development efforts. Cross discipline collaboration with Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts. Overall contribution to design, simulation, verification, integration & test of complex, high speed products.

Basic Qualifications
Bachelor of Science or higher from an accredited college in Computer Engineering, Electrical Engineering or related discipline, or equivalent experience/combined education.
Experience in the verification of any of the following: Digital ASICs/FPGAs, Mixed-signal ASICs/FPGAs
HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
Posses a Secret or Top Secret clearance.

Desired Skills
Experience in leading or managing ASIC projects.
Demonstrated self-starter and voracious learner High EQ (Emotional Intelligence).
Space system design experience.
Understanding of system and hardware requirements related to space.
Customer-facing communication experience (product/services sales, marketing, field, etc.).
Proficient in AI prompting as it applies to this position and practice.

Custom Fields:
Name: OT Status
Value: Exempt

Name: Worksite Classification
Value: Worker will work Onsite Full Time

Name: Security Clearance
Value: Secret

Name: Opportunity for FTE Hire
Value: Yes

Name: Security Clearance Comments
Value: Preference to hire those with existing Secret Clearance, but will take candidates who are willing, capable of obtaining clearance.

Name: Does this role require access to ECI information
Value: Yes

Name: Allow Expenses
Value: No

Name: Work Schedule
Value: 5/40-1st Shift

FPGA Design/Verification Engineer · First Tek, Inc.

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