SOC Timing Engineer

Altera

🇲🇾 Malaysia

On-site

2 months ago

FPGA

2 months ago

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Job Details:

Job Description:

As an STA design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.
Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure

Qualifications:

Experience in Static timing analysis , and industry standard EDA tools like Primetime/PTPX

- Good understanding of timing constraints, clocking, PVT etc

- Should have tapeout experience including in latest technology 10nm or lower

- BE/MS/Phd in Electronics/Electrical Engineering with 3+ Years' experience in physical design and timing closure/signoff

-Candidate should be strong in communication, problem solving and analytical skill

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

SOC Timing Engineer · Altera

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