Engineering - RTL Design Engineer 5

LanceSoft Inc

🇨🇦 Canada

On-site

2 months ago

$75.00 – $87.47 / hour

Verilog

2 months ago

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Job Description: JOB DUTIES: Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation.EDUCATION: Bachelor's or Master's in Computer Engineering. 10+ years of experience.

Engineering - RTL Design Engineer 5 · LanceSoft Inc

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