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EI

Engineer, Staff|6155

eTeam Inc.
  • 🇺🇸 United States
  • On-site
  • Staff / Principal
  • 8 months ago
  • $80 / hour
  • PCIe
  • AI/ML
  • IoT
  • SystemVerilog
  • Python
  • Perl
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Job Title - Senior Staff Engineer
Location - San Diego CA
Duration - 12 Months


General Summary:

Join Client's design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support.

Responsibilities:

  • Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.
  • Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality.
  • Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
  • Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation.
  • From scratch VIP development experience for Serdes controller + PHY is an additional plus

Preferred Qualifications:

  • Experience with Low power design verification, Formal verification and Gate level simulation.
  • Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.,
  • Experience in scripting languages (Python, or Perl).
  • Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Top 5 Required Skills
1. Knowledge of a HVL methodology like SystemVerilog/UVM.
2. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.
3. TBD
4. TBD
5. TBD

Technologies
• Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.,

Education Requirement
• Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Required Years of Experience
• 2+ years ASIC design verification, or related work experience.

Engineer, Staff|6155 · eTeam Inc.

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