DFT Engineer

Job Title: DFT Engineer

Location: Bay Area, CA (Onsite)

Job Overview

Seeking experiencedDFT Engineers to work on cutting-edge semiconductor and AI SoC programs. The ideal candidate should have strong expertise in Design for Test (DFT) methodologies and hands-on experience with industry-standard DFT tools and technologies.

Key Responsibilities

• Design and implement Design for Test (DFT) solutions for complex SoCs.
• Develop and integrate Scan, ATPG, MBIST, and LBIST architectures.
• Perform DFT implementation, verification, and validation activities.
• Generate and analyze ATPG patterns for manufacturing test coverage.
• Debug DFT-related issues and optimize test coverage.
• Collaborate with RTL, Physical Design, and Verification teams throughout the chip development lifecycle.
• Support silicon bring-up and manufacturing test activities.
• Develop and maintain DFT documentation and test methodologies.

Required Skills

• Strong experience in Design for Test (DFT).
• Hands-on experience with:
  • Scan
  • ATPG
  • MBIST
  • LBIST
• Experience with industry-standard DFT tools:
  • Siemens Tessent
  • Synopsys TestMAX
  • Cadence Modus
• Strong understanding of semiconductor design flow and AI SoC development.
• Excellent debugging, problem-solving, and analytical skills.

Work Environment

• Onsite role in the Bay Area, California.
• Opportunity to work on cutting-edge semiconductor and AI SoC programs.