Design Verification Engineer - Cellular SoC
- 🇺🇸 United States
- On-site
- 4 days ago
- $129,300 – $194,700
- SoCs
- SystemVerilog
- Python
- C++
- Java
- Object Oriented Programming
Summary
Do you have a passion for invention and self-challenge? Do you thrive with pushing the limits of what’s considered feasible? As part of an outstanding `team, you’ll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a single, coordinated design. Join us, and you’ll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs!
Description
You will have the opportunity to contribute to the verification effort of a set of sophisticated SOCs delivering the Cellular solution. You will integrate multiple sophisticated IP level DV environments, craft highly reusable outstanding UVM based test bench, implement effective coverage driven and advised test suites, deploy new tools and methodologies to deliver chips that are right-first-time. By collaborating with other product development groups across Apple, you can push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world!
Responsibilities
- You will learn all aspects of a large scale SOC design, Sophisticated verification test benches, different types of SOC architectures, multiple high speed protocols, industry-standard low power architecture, outstanding DV methodology, verification on accelerated platforms, knowledge on Cellular protocol, FW- HW interactions, complexities of multi-chip SOC debug architecture, etc.
Minimum Qualifications
- BS is required.
- Programming experience in SystemVerilog, Python, C++ or Java.
Preferred Qualifications
- MS in EE or CS preferred.
- Coursework in Digital Design, Computer Architecture, Object Oriented Programming, Networking Protocol is a plus.
- Should be an extraordinary teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.
Design Verification Engineer - Cellular SoC · Apple