Design Verification (all experience ranges)

Tylsemi

🇮🇳 India | 🇺🇸 United States
Hybrid
Senior
7 months ago

SoCs
SystemVerilog
triage
Python
Perl
AI
FPGA
PCIe

7 months ago

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## About TylsemiTylsemi is building and scaling high-impact semiconductor operations. We partner across design, manufacturing, and supply chain to bring silicon from concept to high-volume production with speed, quality, and predictable execution.## Role OverviewAs a Design Verification Engineer at Tylsemi, you will help ensure functional correctness, robustness, and tapeout readiness of complex IPs and SoCs. You’ll work closely with design, architecture, firmware, and validation teams to build scalable verification environments, drive coverage closure, and deliver high-signal debug. This role is open across experience levels (0–30 years) and is ideal for engineers who enjoy rigorous problem solving, automation, and building verification flows that scale across programs.## What You’ll Do* Own verification execution for IP and/or SoC blocks from testplan through signoff: bring-up, regressions, coverage, and closure* Develop and maintain verification environments (e.g., SystemVerilog/UVM or equivalent methodologies aligned to the project needs)* Create high-quality testplans: requirements traceability, scenario definition, corner cases, and measurable coverage goals* Write directed and constrained-random tests; build reusable sequences, scoreboards, monitors, and checkers* Drive functional coverage and code coverage closure; identify gaps and propose targeted stimulus and assertions* Debug failures across simulation and emulation/prototyping (as applicable): isolate root cause, propose fixes, and validate resolution* Build and scale regression infrastructure: test selection, triage workflows, failure bucketing, and signal-to-noise improvements* Automate repetitive verification tasks (Python/Perl/Tcl/Make or similar) to improve predictability and turnaround time* Leverage AI-assisted tools to accelerate debug, log triage, test generation, and documentation—while maintaining engineering rigor and reproducibility* Partner with design/architecture to clarify specs, review micro-architecture, and prevent ambiguity-driven bugs* Contribute to tapeout readiness: signoff checklists, documentation, and postmortems that improve future execution## What We’re Looking For* Strong verification fundamentals: ability to translate specs into a clear, reviewable testplan and measurable closure criteria* Debug mindset: structured problem statements, data-driven root cause, and clean reproduction steps* Comfort building automation and maintaining regression health over time (not just writing tests)* Good engineering hygiene: readable code, version control discipline, and documentation that supports cross-team execution* Collaboration skills across design, DV, firmware, and validation to drive closure without late-stage surprises## Required Skills* Design verification experience across any level (entry to senior), aligned to role scope* Automation for verification productivity (scripting, tooling, CI/regression workflows)* Regression ownership: triage, stability, failure analysis, and continuous improvement* Practical use of AI tools to improve DV throughput (e.g., log summarization, test scaffolding, debug assistance) with appropriate review and validation## Nice to Have* SystemVerilog/UVM, assertions (SVA), and formal verification exposure* Experience with emulation and/or FPGA prototyping flows and debug* SoC-level verification experience: interconnects, coherency, interrupts, power management, boot flows* Verification of common interfaces (e.g., AXI/AHB/APB, PCIe, USB, Ethernet, DDR/LPDDR) depending on program needs* Experience improving verification infrastructure: test frameworks, coverage dashboards, failure bucketing, or performance optimization## Success in This Role Looks Like* Clear, measurable verification closure with strong coverage and minimal late-stage churn* Stable, high-signal regressions with fast triage and low noise* Repeatable, well-documented verification deliverables that scale across projects and teams* Proactive risk identification and crisp cross-functional communication that prevents surprises near tapeout## Location* Bengaluru, India* International## Experience0–30 years (scope and ownership will be aligned to experience level).

Design Verification (all experience ranges) · Tylsemi

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