LI
Design For Test (DFT) Engineer
Leadstack Inc
- Location not stated
- 23 hours ago
- $100 – $130 / hour
- Perl
- Python
- Verilog
- SystemVerilog
23 hours ago
LeadStack Inc. is an award winning, one of the nation's fastest growing, certified minority owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Workwe're proud to partner with some of the most admired Fortune 500 brands in the world.
Design For Test (DFT) Engineer
Duration: 6+months
Location: Onsite San Jose, CA - 5 days a week
Description
The team is looking for a Design-for-Test contractor to test and validate next-generation chips. Candidate will work with Front End and Physical Design teams to implement DFT and test designs impacting product lines for radio frequency (RF) and Bluetooth/Wireless LAN chipsets.
Job Responsibilities:
- Experience with memory BIST – Siemens Tessent Flow
- Experience with gate-level simulation and simulation debug
- Experience with automation and scripting – Tcl/Perl/Python
- Experience with scan compression – SEQ/Ultra/TestKompress
- Experience with ATPG – Tetramax
- Experience with ATPG diagnosis, ATE debug and silicon bring up
- DFT pattern translation – VTRAN
- Experience with RTL design – Verilog/SystemVerilog
- Some experience with STA and timing analysis concepts – PrimeTime (CDC, clock gating checks, timing constraints)
Required Skills And Experience:
- 5+ years relevant industrial DFT experience
- Excellent problem solving and debugging skills
- Ability to complete assignments independently
know more about current opportunities at LeadStack , please visit us on https://leadstackinc.com/careers/
Should you have any questions, feel free to call me on (513) 3184502 or send an email on waseem.ahmad@leadstackinc.com
Design For Test (DFT) Engineer · Leadstack Inc