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Design Engineer II

Cadence
  • 🇮🇳 India
  • 1 day ago
  • Verilog
  • Perl

Not enough detail in this posting to match

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

BE/BTECH/ME/MTECH

Job Description

2-5 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification Expertise in test-bench development Strong RTL and GLS (w/ or w/o SDF) sim debug skills Should be able to manage project schedule and delivery independently

Should be good in Perl/Tcl scripting and automation

We’re doing work that matters. Help us solve what others can’t.

Design Engineer II · Cadence

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