Device Development Senior Staff Engineer

This Device Development Senior Staff Engineer will design, develop, and support new and existing CMOS-based offerings in a technologist or device engineering role.

Major Areas of Accountability:

• New device development, transfer, and integration in a manufacturing environment.
• Develop design rules, electrical targets, and related technology requirements
• Liaison with Design Enablement group on matters relating device requirements and PDK development for CMOS-compatible technologies as needed to support SkyWater foundry technologies.
• Lead development of device test chips and characterization to support the above technology developments.
• Perform targeting and yield analysis to advance product maturity
• Provide Subject Matter Expert guidance to customers and SkyWater colleagues as needed to address questions and concerns with technology elements and device issues.

Required Qualifications:

• 7-10 years experience with BS, 5-7 years experience with MS, 2+ years experience with PhD in Engineering, Physics, or related field.
• Comprehensive knowledge of device performance, optimization, and yield limiters relevant to deep-submicron CMOS-compatible technologies.
• Deep understanding of typical IC process design.
• Expertise in device characterization to enable process and modeling requirements.
• Expertise in dealing with both internal and external customers.
• Clear problem-solving capability, data driven, inventive solution oriented. Able to articulate thought processes in both technical and business settings.
• Knowledge of DOE, SPC, and 6-sigma concepts and applications.
• U.S. Person Required:This position requires compliance with the International Traffic in Arms Regulations (ITAR). All accepted applicants must be U.S. Persons. ITAR defines a U.S. Person as U.S. citizen, U.S. Permanent Resident, Political Asylee, or Refugee.

• At least (7) years of advanced device development experience.
• Experience in project technology transfers into or out of a semiconductor foundry.
• Experience with test chip layout and validation in a Cadence environment.
• 2-3 years of Project Management skills and/or defined training.
• Background in physics-based device simulation, design, and characterization for topics such as PEX, TCAD, noise, ESD mitigation, and stress
• Experience in DOE and CMOS device design for extreme environments such as cryogenic, radiation, or high temperature.