Associate III - VLSI PDK

Requirements: Experience in Cadence Platform Knowledge of layout concepts like Matching, shielding, Symmetry, ESD, latch-up, Reliability and DFM PDK and rule-set development understanding Working experience in blocks like high speed IO, Charge pumps, Regulators, semi-custom blocks etc. Scripting knowledge a plus: PERL and SKILL Good communication (written and verbal) and interpersonal skills Excellent working ability with circuit design and layout methodology development teams Excellent problem-solving skills Responsibilities: Handling block layouts like AMS, Charge Pumps, I/O’s, Reference generator Interaction with project lead (design and layout) and CAD for various requirements Complete all the tasks as defined by the leads on time.