Associate III - VLSI PD SMG

Title: OS Engineer for PNR Methodology Role and Responsibilities: Place-and-route (PD) Flow development and support Skill Requirements: Tools : Innovus, FC tools hands-on experience Methodology : Develop and support the execution of the full physical design flow, including Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), and Routing, DRC analysis, Timing & functional ECO Automation Development : Develop and maintain automated design flows to reduce TAT (Turn-Around Time) and minimize manual errors. Custom Tooling : Utilize scripting languages (Tcl, Python, or Perl) to create custom scripts for data extraction, report parsing, and tool orchestration. Flow Optimization : Implement DOE (Design of Experiments) to determine optimal tool settings and repeater conditions for minimized clock latency and improved power. Root Cause Analysis : Debug complex timing violations, congestion issues, DRC & electromigration (EM) failures etc Scripting : Advanced proficiency in Tcl (essential for Innovus) and Python/Perl . Education : Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Good to have: Worked on the flow development and support. Hands-on on the LEC, extraction, STA & PV. Hands-on with Genus synthesis Experience: 5-8 years Qualifications: B.Tech/B.E/M.Tech/M.E