JD- DFT Role and Responsibilities: Person will be responsible for scan insertion, stuck_at & at-speed ATPG, scan simulations and post silicon debugging for hierarchical design. Skill Requirements: Person should have good hands-on experience in SCAN, ATPG , Scan pattern verification and also should have good understanding of scan constraints. Good to have: Knowledge of MBIST. Experience: 5- 10 yrs Qualifications: B.Tech/M.Tech B.Tech/B.E/M.Tech/M.E
Associate III - VLSI DFT SMG · UST