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U

Associate III - VLSI

UST
🇮🇳 India
On-site
2 months ago
  • C++
  • SystemVerilog

Not enough detail in this posting to match

UST Job Title: Associate III - VLSI

At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact—touching billions of lives in the process. Visit us at.

The Opportunity:

UST is looking for Verification Engineer

Responsibilities:

  • Hands on verification experience with C/C++/SystemVerilog testbench development.
  • Hands on experience with coverage planning, coding and coverage closure.
  • Experience with x86, ARM or any other industry standard microprocessor ISA.
  • Experience with Cache, Coherency and Data-Consistency verification.
  • Experience in clocking, reset, power-up sequences and power management verification.
  • Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.
  • Understanding of low power design verification techniques is a plus.

What we believe:

We’re proud to embrace the same values that have shaped UST since the beginning. Since day one, we’ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.

Humility:

We will listen, learn, be empathetic and help selflessly in our interactions with everyone.

Humanity:

Through business, we will better the lives of those less fortunate than ourselves.

Integrity:

We honour our commitments and act with responsibility in all our relationships.

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.

All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.


UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.

• To support and promote the values of UST.

• Comply with all Company policies and procedures

Associate III - VLSI · UST

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