ASIC Design Engineer — Neural Engine DMA

Summary

Computational photography, live language translation, and countless other on-device AI

capabilities depend on moving enormous amounts of data between memory and compute at

exactly the right time. As part of our Silicon Engineering Group, you will own the design

of high-performance DMA engines responsible for moving model weights and activation tensors

between the memory subsystem and the Apple Neural Engine.

In this role, you will take end-to-end ownership of DMA subsystem blocks and collaborate

closely with architecture and verification teams across the full front-end design cycle.

The work you deliver ships in Apple products used by billions of people every day.

Description

As an ASIC Design Engineer on the ANE DMA Design team, you will own the design of DMA

subsystem blocks from microarchitecture specification through tapeout. ANE DMA's scale

and complexity means grappling with: fetch sequencing, out-of-order response management,

memory system back-pressure, address translation integration, and pipeline hazard

resolution. In this front-end design role, your work will include:

- Taking end-to-end ownership of DMA blocks through the full cycle: microarchitecture

specification, RTL implementation, front-end signoff (synthesis, timing

closure, area and power analysis, linting, LEC), and design verification closure.

- Writing well-parameterized RTL structured for correct synthesis, clean timing, and low

power, along with assertions and cover points that encode design intent and ensure

verification completeness.

- Collaborating with fellow designers, architecture, and physical implementation teams to

explore microarchitectural trade-offs and drive solutions that meet performance, power,

and area targets.

- Working closely with design verification and formal verification teams to ensure

functional correctness: reviewing test plans, debugging failures, and ensuring the

design's intended behavior is fully exercised.

Minimum Qualifications

• Bachelors Degree plus 3 years of industry experience

Preferred Qualifications

• Experience designing SoC front-end RTL in Verilog or SystemVerilog through at least
• one tapeout, including tasks such as synthesis, timing closure, area and power analysis,
• linting, and logic equivalence checks.
• Experience designing DMA microarchitecture: address sequencing, flow control,
• arbitration, or transaction ordering.
• Experience with on-chip bus protocols (AMBA AXI, AHB, APB) and on-chip interconnect
• fabrics.
• Background in adjacent domains: hardware compression, networking SoCs, image and video
• processing, multimedia, or AI/ML accelerators.
• Experience writing precise micro-architectural specifications.
• Familiarity with scripting languages (Python, Perl, Tcl) for design automation.