RTL Design Lead

Required Skills & Experience:

• Expertise in SoC subsystem/IP design.
• Strong experience in IP design, subsystem/cluster design, and SoC-level integration using Verilog/SystemVerilog.
• In-depth knowledge of RTL quality checks, including Lint and CDC.
• Good understanding of AMBA bus protocols such as AXI, AHB, ATB, and APB.
• Good understanding of timing concepts.
• Knowledge of synthesis and low-power design is a plus.
• Knowledge of one or more interface protocols.