Senior Staff Engineer - AMS IP Verification

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

What You Can Expect

•Driveend‑to‑end verification ownership for complexSerDes / AMS / mixed‑signal IPs across advanced nodes (5nm, 3nm, 2nm).

•Lead verification ofhigh‑speed interfaces including SerDes, PCIe, Ethernet, DDR, D2D, PAM4/PAM2‑based designs.

•Define and execute verification plans coveringcalibration, link training, power modes, analog‑digital interaction, and firmware‑driven flows.

•Debug and resolve complex issues spanningRTL, AMS models, firmware, VIPs, and system‑level behaviors.

•Drivecoverage closure, regression stability, and sign‑off readiness with high quality standards.

•Own or co‑ownGate‑Level Simulation (GLS), power‑aware verification, CDC/RDC validation, and timing‑aware checks.

•Collaborate closely withDesign, Architecture, Firmware, and Silicon teams to ensure early alignment and risk mitigation.

•Contribute toverification infrastructure, checkers, automation, and reusable frameworks.

•Mentor junior engineers and act as atechnical role model within the team.

•Identify opportunities to improveproductivity and quality, including use ofautomation or AI‑assisted verification tools.

What We're Looking For

The Senior Staff Engineer is ahighly experienced hands‑on technical contributor who drives complex verification and AMS bring‑up efforts while influencing verification strategy and execution quality across projects. This role combinesdeep domain expertise, strong ownership, and cross‑team collaboration, with growing responsibility for technical direction and mentoring.
 

Required Technical Qualifications

• 8–12 years of hands‑on experience inverification and/or AMS systems.

•Strong expertise inSystemVerilog, UVM, and modern verification methodologies.

•Deep understanding of:

    • SerDes / PHY architectures

    • AMS and mixed‑signal verification

    • Calibration and link training flows

    • Register models and firmware interaction

•Experience integrating and usingindustry VIPs (Synopsys, Cadence, Siemens/Mentor, Avery).

•Proven ability to debug difficult issues acrossmultiple abstraction layers.

•Solid understanding ofsystem‑level behavior and trade‑offs, not just block‑level execution.

Leadership & Behavioral Expectations

•Demonstratesstrong technical ownership and reliability.

•Leads by example throughhands‑on execution and disciplined problem solving.

•Communicates technical issues clearly to diverse stakeholders.

•Makes sound decisions under ambiguity with a quality‑first mindset.

•Actively supports team growth throughmentoring and knowledge sharing.

•Begins to influencetechnical direction and best practices beyond individual tasks.

Nice‑to‑Have / Differentiators

•Experience acrossmultiple technology nodes and IP generations.

•Contributions toverification methodology improvements or reusable infrastructure.

•Exposure topost‑silicon debug and correlation.

•Participation ininternal tech forums, papers, or conferences (DVCon, VLSI‑D, internal reviews).

Success Criteria

•Consistently delivers complex verification areas withhigh quality and minimal rework.

•Reduces integration and silicon risk through proactive technical engagement.

•Becomes ago‑to technical expert within the domain.

•Scales impact by enabling others, not just individual execution.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit ourCareers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.