RC
Lead Product validation Eng
RAPS Consulting - India
🇮🇳 India
On-site
Staff / Principal
11 months ago
- Verilog
- Perl
- Python
11 months ago
Education and experience: B.Tech/B.E/ M. Tech / M.E in Electrical/Electronics/Computer Engineering having 2 yrs relevant experience Knowledge of STA, SI, Delay calculation, Timing DRV, ECO (automated and manual), timing constraints, report_timing commands, timing analysis, Verilog and debug skills. Able to envision the automation requirements and execute it in one of the scripting languages like Perl, TCL, Python or C Shell Familiar with front-end / back-end design flow knowledge of design Knowledge of Physical Design Implementation platforms like INNOVUS
Lead Product validation Eng · RAPS Consulting - India