Principal Design Engineer

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Role Summary

We are looking for an experiencedPrincipal Analog Design Engineer to drive the design and delivery ofhigh‑speed interface IPs, with a strong emphasis onDie‑to‑Die (D2D) interconnects based on the UCIe standard andadvanced package technologies. The role requires hands‑on ownership fromarchitecture through silicon bring‑up, working closely with layout, verification, package, and system teams.

Key Responsibilities

• Architect, design, and deliverhigh‑speed analog / mixed‑signal circuits for Die‑to‑Die and chiplet‑based systems, including UCIe‑compliant interfaces.
• Own analog blocks forhigh‑speed interfaces such as clocking, TX/RX front‑ends, termination schemes, biasing, and equalization support circuits.
• Drivearchitecture definition, feasibility analysis, and design trade‑offs considering signal integrity, power, noise, and packaging parasitics.
• Performschematic design, simulation, and optimization across PVT corners using industry‑standard EDA tools.
• Work closely withadvanced package teams (2.5D / 3D, interposers, organic substrates) to co‑optimize circuit and package design.
• Supportlayout reviews, parasitic extraction analysis, and post‑layout sign‑off for high‑speed performance.
• Collaborate withAMS verification, digital, and system teams to enable full‑chip integration and validation.
• Participate insilicon bring‑up, debug, and characterization, including correlation with simulation results.
• Contribute todesign methodology, checklists, and best practices for high‑speed analog and D2D designs.

Required Qualifications

• Bachelor’s or Master’s degree inElectrical / Electronics Engineering or related field.
• 8+ years of hands‑on experience inanalog / mixed‑signal IC design.
• Strong experience withhigh‑speed interface design (e.g., DDR, PCIe, SerDes, Die‑to‑Die links).
• Solid understanding ofUCIe standard concepts, D2D PHY requirements, and chiplet architectures.
• Experience working withadvanced packaging technologies and understanding package‑induced effects on high‑speed signaling.
• Proficiency inschematic‑level design, simulation, and debug across PVT corners.
• Strong fundamentals inanalog circuit theory, signal integrity, noise analysis, and clocking.

Preferred / Nice‑to‑Have Skills

• Direct hands‑on experience withUCIe PHY design or integration.
• Exposure toAMS verification flows and mixed‑signal simulation environments.
• Experience withpost‑silicon debug and correlation.
• Knowledge ofpower integrity, thermal considerations, and package‑aware design flows.
• Ability to mentor junior engineers and lead technical discussions.

What Success Looks Like

• Robust, scalableUCIe / D2D analog IPs meeting performance, power, and reliability targets.
• Smooth collaboration acrossdesign, verification, and packaging teams.
• Predictable execution aligned withproject milestones and KPIs / OKRs.
• Strong ownership mindset fromarchitecture to silicon.

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