Senior/Lead SoC Emulation Engineer

Senior Emulation Engineer – VELOCE / ZEBU / Palladium (Automotive SoC)

NXP is looking for a STAFF‑level Emulation Engineer with5–10 years of hands‑on experience in SoC emulation to work oncutting‑edge automotive MCUs/SoCs. This role focuses onleading pre‑silicon validation and software execution onindustry‑leading emulation platforms for advanced,low‑power automotive designs.

Key Responsibilities

• LeadSoC‑level emulation bring‑up, execution, and debug on
  Mentor/Siemens VELOCE, Synopsys ZEBU, and Cadence Palladium
• Ownemulation build creation, configuration, partitioning, and optimization for complex automotive SoCs
• Enable and debugpre‑silicon software flows usingJTAG / SWD interfaces andLTB or any other  debuggers
• Executeapplication‑specific automotive use cases including boot flows, peripherals, power modes, and safety scenarios on emulation builds
• Drivelow‑power validation and debug, including power‑up/power‑down sequences
• Debug and validateclock and reset architectures, including clock trees, clock gating, reset sequencing, and cross‑domain interactions
• Enable and debugmulti‑core ARM boot flows, including primary/secondary core bring‑up, synchronization, and hand‑off sequences
• Collaborate closely withRTL, SoC verification, firmware, system, and IP teams
• Providetechnical leadership and mentoring across emulation activities and methodologies

Required Skills & Experience

• 3–6 years of experience in SoC Emulation, with strong hands‑on exposure to
  Synopsys ZEBU, Mentor/Siemens VELOCE, and/or Cadence Palladium
• Proven expertise inemulation build generation, bring‑up, and execution
• Strong debugging skills usingJTAG / SWD andLTB debuggers
• Hands‑on experience working onARM‑based automotive SoCs, including
  Cortex‑M7, Cortex‑M4, Cortex‑M0+, and Cortex‑R52 cores
• Solid understanding ofclocking and reset architectures, including reset dependency modeling and clock domain interactions
• Strong knowledge ofmulti‑core ARM booting concepts, core enablement, reset vectors, and inter‑core coordination
• Solid understanding oflow‑power SoC/MCU architectures, power states, clocks, and resets
• Ability to execute and debugrealistic software and application workloads on emulation
• SoC Verification experience (UVM / simulation / regression debug) is a strong plus

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