Associate III - VLSI Analog Layout

Required Skills 4–8 years of hands-on experience in Analog, Mixed-Signal, and I/O Layout design. Strong experience with advanced TSMC and Samsung technology nodes (2nm, 3nm, and 5nm). Hands-on experience in the layout of one or more of the following: SerDes Transmitter (TX) Receiver (RX) LDO Bandgap Reference (BGR) Operational Amplifier (Op-Amp) ADC PLL HSIO GPIO DDR I/O Experience in custom layout methodologies, tools, and design flows. Strong knowledge of layout techniques, including device matching, common centroid, shielding, guard rings, EM/IR, and layout-dependent effects (LDE). Experience with physical verification including DRC, LVS, ERC, and PEX. Good understanding of semiconductor manufacturing processes and layout optimization techniques. Preferred Tools Cadence Virtuoso Layout Suite Calibre (DRC/LVS/PEX) Custom layout automation tools and verification flows Qualifications Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related discipline.