Experienced Digital Physical Design Engineer with strong expertise inSynthesis, Place & Route (PnR), Static Timing Analysis (STA), and ECO implementation. Proven ability to drive timing closure, fix setup/hold violations, and optimize designs for performance and area. Hands-on experience with industry-standard EDA tools, constraint development, and debugging across multiple modes and corners. Collaborative team player skilled in working with RTL, DFT, and signoff teams to ensure successful design convergence and tapeout readiness.
More information about NXP in India...
#LI-2734
